Enhanced clustered voltage scaling for low power
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ACM Press
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs;2022 IEEE 3rd International Conference on Electronics, Control, Optimization and Computer Science (ICECOCS);2022-12-01
2. Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI;VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things;2019
3. A Four-Transistor Level Converter for Dual-Voltage Low-Power Design;Journal of Low Power Electronics;2014-12-01
4. Placement for Power Optimization;Closing the Power Gap Between ASIC & Custom;2007
5. Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2005-09
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