Tutorial: How to Use Model Checking to Analyze Circuits at the Transistor Level

Author:

Raitza Michael1ORCID,Märcker Steffen1ORCID

Affiliation:

1. Faculty of Computer Science, Department of Computer Engineering, Chair of Processor Design, TU Dresden, Dresden, Saxony, Germany

Publisher

ACM

Reference6 articles.

1. Christel Baier and Joost-Pieter Katoen. 2008. Principles of model checking. MIT Press. isbn: 978-0-262-02649-9.

2. Fifteen Years of Formal Property Verification in Intel

3. Reconfigurable Silicon Nanowire Transistors

4. Jayanand Asok Kumar, Lingyi Liu, and Shobha Vasudevan. 2011. Scaling probabilistic timing verification of hardware using abstractions in design source code. In 2011 Formal Methods in Computer-Aided Design, FMCAD '11. (Oct. 2011), 196--205.

5. Michael Raitza, Steffen Märcker, Shubham Rai, and Akash Kumar. 2022. Exploring standard-cell designs for reconfigurable nanotechnologies: a formal approach. In Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe (DATE '22). European Design and Automation Association, Antwerp, Belgium, 23--28. isbn: 9783981926361.

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