Porting a JIT Compiler to RISC-V: Challenges and Opportunities

Author:

Ducasse Quentin1,Polito Guillermo2,Tesone Pablo2,Cotret Pascal1,Lagadec Loïc1

Affiliation:

1. Lab-STICC, ENSTA Bretagne, France

2. Inria / CNRS, University of Lille, France / France / France

Publisher

ACM

Reference12 articles.

1. Andrew P Black Oscar Nierstrasz Stéphane Ducasse and Damien Pollet. 2010. Pharo by example. Lulu. com. Andrew P Black Oscar Nierstrasz Stéphane Ducasse and Damien Pollet. 2010. Pharo by example. Lulu. com.

2. The structure and performance of efficient interpreters;Ertl M Anton;Journal of Instruction-Level Parallelism,2003

3. GCC. 2022. GCC li pseudoinstruction cost functions implementation. https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/riscv/riscv.c;h=a545dbf66f734855090568ce1a253b373345eec0;hb=HEAD#l395 GCC. 2022. GCC li pseudoinstruction cost functions implementation. https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/riscv/riscv.c;h=a545dbf66f734855090568ce1a253b373345eec0;hb=HEAD#l395

4. Garth Gillespie. 2018. LuaJIT SSA IR 2.0. http://wiki.luajit.org/SSA-IR-2.0#introduction_example-ir-dump Garth Gillespie. 2018. LuaJIT SSA IR 2.0. http://wiki.luajit.org/SSA-IR-2.0#introduction_example-ir-dump

5. Optimizing dynamically-typed object-oriented languages with polymorphic inline caches

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1. RISC-V for Genome Data Analysis: Opportunities and Challenges;2023 38th Conference on Design of Circuits and Integrated Systems (DCIS);2023-11-15

2. Gigue: A JIT Code Binary Generator for Hardware Testing;Proceedings of the 15th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages;2023-10-18

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