Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection

Author:

Zhu Xian1,Wernsman Robert1,Zambreno Joseph1

Affiliation:

1. Iowa State University, Ames, Iowa, USA

Publisher

ACM

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs;2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT);2023-10-21

2. OSM: Off-Chip Shared Memory for GPUs;IEEE Transactions on Parallel and Distributed Systems;2022-12-01

3. DTexL: Decoupled Raster Pipeline for Texture Locality;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10

4. Locality-Aware CTA Scheduling for Gaming Applications;ACM Transactions on Architecture and Code Optimization;2022-03-31

5. Compiler-Assisted GPU Thread Throttling for Reduced Cache Contention;Proceedings of the 48th International Conference on Parallel Processing;2019-08-05

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