High-Performance Cryptographic SoC Virtual Prototyping Platform Based on RISC-V VP-Reference-Cited by-同舟云学术

High-Performance Cryptographic SoC Virtual Prototyping Platform Based on RISC-V VP

Published:2022-06-23 Issue: Volume: Page:
ISSN:
Container-title:2022 6th International Conference on High Performance Compilation, Computing and Communications (HP3C)
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Author:

Wu Junwei¹,Zheng Xin²,Zeng Shaofen¹,Gao Huaien²,Xiong Xiaoming²

Affiliation:

1. School of Automation, Guangdong University of Technology, China

2. School of Integrated Circuits, Guangdong University of Technology, China

Funder

GuangDong Basic and Applied Basic Research Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3546000.3546013

Reference17 articles.

1. Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration

2. Asanović K, Patterson D A. 2014. Instruction Sets Should Be Free : The Case for RISC-V. EECS Department , University of California , Berkeley, Tech . Rep. UCB/EECS- 2014 -146. Asanović K, Patterson D A. 2014.Instruction Sets Should Be Free: The Case for RISC-V. EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-146.

3. System simulation with PULP virtual platform and SystemC

4. Màrius Montón . 2020 . A RISC-V SystemC-TLM simulator. arXiv:2010.10119 [cs] (October 2020) . Retrieved May 11, 2022 from http://arxiv.org/abs/2010.10119 Màrius Montón. 2020. A RISC-V SystemC-TLM simulator. arXiv:2010.10119 [cs] (October 2020). Retrieved May 11, 2022 from http://arxiv.org/abs/2010.10119

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