Affiliation:
1. The University of British Columbia, Vancouver, BC, Canada
Abstract
CAD tool designers are always searching for more benchmark circuits to stress their software. In this article we present a heuristic method to generate benchmark circuits specially suited for incremental place-and-route tools. The method removes part of a real circuit and replaces it with an altered version of the same circuit to mimic an incremental design change. The alteration consists of two steps:
mutate
followed by
perturb
. The perturb step exactly preserves as many circuit characteristics as possible. While perturbing, reproduction of interconnect locality, a characteristic that is difficult to measure reliably or reproduce exactly, is controlled using a new technique,
ancestor depth control
(ADC). Perturbing with ADC produces circuits with postrouting properties that match the best techniques known to-date. The mutate step produces targetted mutations resulting in controlled changes to specific circuit properties (while keeping other properties constant). We demonstrate one targetted mutation heuristic, scale, to significantly change circuit size with little change to other circuit characteristics. The method is simple enough for inclusion in a CAD tool directly, and fast enough for use in on-the-fly benchmark generation.
Publisher
Association for Computing Machinery (ACM)
Cited by
3 articles.
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1. FPGA Architecture Exploration for DNN Acceleration;ACM Transactions on Reconfigurable Technology and Systems;2022-05-10
2. Advancing Placement;Proceedings of the 2021 International Symposium on Physical Design;2021-03-21
3. Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation;ACM Transactions on Embedded Computing Systems;2012-08