Enabling transparent hardware acceleration on Zynq SoC for scientific computing

Author:

Stornaiuolo Luca1,Carloni Filippo1,Pressiani Riccardo1,Natale Giuseppe1,Santambrogio Marco1,Sciuto Donatella1

Affiliation:

1. Politecnico di Milano, Milan, Italy

Abstract

In a quest for making FPGA technology more accessible to the software community, Xilinx recently released PYNQ, a framework for Zynq that relies on Python and overlays to ease the integration of functionalities of the programmable logic into applications. In this work we build upon this framework to enable transparent hardware acceleration for scientific computations for Zynq. We do so by providing a custom NumPy library designed for PYNQ, as it is the de-facto scientific library for Python. We then demonstrate the effectiveness of the proposed approach on a biomedical use case involving the extraction of features from the Electroencephalography (EEG).

Publisher

Association for Computing Machinery (ACM)

Subject

Engineering (miscellaneous),Computer Science (miscellaneous)

Reference17 articles.

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Improved Implementation of PYNQ-Based FFT Hardware Accelerator;2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT);2024-03-15

2. ZyPy: Intercepting NumPy operations for acceleration on FPGAs;Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies;2023-06-14

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