A Novel ReRAM-Based Processing-in-Memory Architecture for Graph Traversal

Author:

Han Lei1ORCID,Shen Zhaoyan1,Liu Duo2,Shao Zili1,Huang H. Howie3,Li Tao4

Affiliation:

1. Hong Kong Polytechnic University, Hong Kong SAR, China

2. Chongqing University, Chongqing, China

3. George Washington University, Washington, DC

4. University of Florida, Gainesville, FL

Abstract

Graph algorithms such as graph traversal have been gaining ever-increasing importance in the era of big data. However, graph processing on traditional architectures issues many random and irregular memory accesses, leading to a huge number of data movements and the consumption of very large amounts of energy. To minimize the waste of memory bandwidth, we investigate utilizing processing-in-memory (PIM), combined with non-volatile metal-oxide resistive random access memory (ReRAM), to improve both computation and I/O performance. We propose a new ReRAM-based processing-in-memory architecture called RPBFS, in which graph data can be persistently stored and processed in place. We study the problem of graph traversal, and we design an efficient graph traversal algorithm in RPBFS. Benefiting from low data movement overhead and high bank-level parallel computation, RPBFS shows a significant performance improvement compared with both the CPU-based and the GPU-based BFS implementations. On a suite of real-world graphs, our architecture yields a speedup in graph traversal performance of up to 33.8×, and achieves a reduction in energy over conventional systems of up to 142.8×.

Funder

National Natural Science Foundation of China

Chongqing High-Tech Research Program

Research Grants Council of the Hong Kong Special Administrative Region, China

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture

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1. An efficient SSSP algorithm on time-evolving graphs with prediction of computation results;Journal of Parallel and Distributed Computing;2024-04

2. Runtime Row/Column Activation Pruning for ReRAM-based Processing-in-Memory DNN Accelerators;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

3. GraphA: An efficient ReRAM-based architecture to accelerate large scale graph processing;Journal of Systems Architecture;2022-12

4. Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases;2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2022-07

5. To PIM or not for emerging general purpose processing in DDR memory systems;Proceedings of the 49th Annual International Symposium on Computer Architecture;2022-06-11

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