Affiliation:
1. University of Toronto, Canada
Abstract
Multicore processors contain new hardware characteristics that are different from previous generation single-core systems or traditional SMP (symmetric multiprocessing) multiprocessor systems. These new characteristics provide new performance opportunities and challenges. In this paper, we show how hardware performance monitors can be used to provide a fine-grained, closely-coupled feedback loop to dynamic optimizations done by a multicore-aware operating system. These multicore optimizations are possible due to the advanced capabilities of hardware performance monitoring units currently found in commodity processors, such as execution pipeline stall breakdown and data address sampling. We demonstrate three case studies on how a multicore-aware operating system can use these online capabilities for (1) determining cache partition sizes, which helps reduce contention in the shared cache among applications, (2) detecting memory regions with bad cache usage, which helps in isolating these regions to reduce cache pollution, and (3) detecting sharing among threads, which helps in clustering threads to improve locality. Using realistic applications from standard benchmark suites, the following performance improvements were achieved: (1) up to 27% improvement in IPC (instructions-per-cycle) due to cache partition sizing; (2) up to 10% reduction in cache miss rates due to reduced cache pollution, resulting in up to 7% improvement in IPC; and (3) up to 70% reduction in remote cache accesses due to thread clustering, resulting in up to 7% application-level improvement.
Publisher
Association for Computing Machinery (ACM)
Cited by
42 articles.
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1. On the impact of hardware-related events on the execution of real-time programs;Design Automation for Embedded Systems;2023-12
2. NUBA: Non-Uniform Bandwidth GPUs;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2023-01-27
3. COMPROF and COMPLACE: Shared-Memory Communication Profiling and Automated Thread Placement via Dynamic Binary Instrumentation;2022 IEEE 29th International Conference on High Performance Computing, Data, and Analytics (HiPC);2022-12
4. Smart scheduler: an adaptive NVM-aware thread scheduling approach on NUMA systems;CCF Transactions on High Performance Computing;2022-10-11
5. Monitoring Collective Communication Among GPUs;Euro-Par 2021: Parallel Processing Workshops;2022