Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines
Author:
Affiliation:
1. Georgia Institute of Technology
2. Intel Labs
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2934583.2934607
Reference17 articles.
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2. K. Tiri etal "A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation " DATE 2004. K. Tiri et al. "A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation " DATE 2004.
3. M Rivain etal "Provably Secure Higher-Order Masking of AES " CHES 2010. M Rivain et al. "Provably Secure Higher-Order Masking of AES " CHES 2010.
4. A. Shamir "Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies " CHES 2000. A. Shamir "Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies " CHES 2000.
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