A logic-based semantics for the verification of multi-diagram UML models

Author:

Baresi Luciano1,Morzenti Angelo1,Motta Alfredo1,Rossi Matteo1

Affiliation:

1. Politecnico di Milano, Milano, Italy

Abstract

UML is a well-known and widely used design notation: it offers a rich set of modeling elements, but their behavior is often not properly defined. Many proposals have tried to provide UML with a formal semantics, but they often focus on a limited number of diagram types, and thus do not provide a viable solution for the actual verification of complex UML models. This paper addresses a significant and consistent set of UML diagrams, called MADES UML, and uses a metric temporal logic to ascribe a formal semantics to them. It also introduces a prototype verification tool based on a bounded model/satis ability checker. The verification of a car collision avoidance system gave encouraging results.

Publisher

Association for Computing Machinery (ACM)

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Faltas en el aprendizaje del modelado de clases y casos de uso: una revisión sistemática;Revista Científica;2023-01-02

2. A Formalization and Transformation Method of UML Model;2022 3rd International Conference on Computing, Networks and Internet of Things (CNIOT);2022-05

3. From Petri Nets to UML: A New Approach for Model Analysis;Advances in Intelligent Systems and Computing;2019

4. A Logic-Based Approach for the Verification of UML Timed Models;ACM Transactions on Software Engineering and Methodology;2017-10-05

5. How bit-vector logic can help improve the verification of LTL specifications over infinite domains;Proceedings of the 31st Annual ACM Symposium on Applied Computing;2016-04-04

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