A multi-microprocessor implementation of a general purpose pipelined CPU

Author:

Ramseyer Richard R.1,Dam Andries van2

Affiliation:

1. Raytheon Submarine Signal Division, Portsmouth, Rhode Island

2. Program in Computer Science, Brown University, Providence, Rhode Island

Abstract

This paper discusses and shows by example the potential of a network of microprogrammable microprocessors as a cost-effective alternative to traditional hardwired medium- and large-scale mainframes. While biased towards vector processing, this system is not intended to compete with multi-million dollar supercomputers such as the 360/195, CDC STAR, Illiac IV, CRAY-1, TI ASC, etc., which use special algorithms and the fastest circuitry available. The architecture incorporates pipelining, multiprocessing and distributed processing techniques with bipolar microprocessor technology. The result should be a machine which will equal or outperform most traditional third- and fourth-generation mainframes at a fraction of the CPU cost. This should be the case even for scalar, general purpose computation.

Publisher

Association for Computing Machinery (ACM)

Reference11 articles.

1. Stotts L.B. "High Speed Optical Matrix Multiplier System" Department of the Navy Washington D.C. May 1975. Stotts L.B. "High Speed Optical Matrix Multiplier System" Department of the Navy Washington D.C. May 1975.

2. The Illiac IV Computer;Barnes G.H.;IEEE Transactions on Computers,1968

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Reconfigurable computer architectures;IEE Proceedings E Computers and Digital Techniques;1982

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