On the reliability of hardware event monitors in MPSoCs for critical domains

Author:

Barrera Javier1,Kosmidis Leonidas2,Tabani Hamid2,Mezzetti Enrico2,Abella Jaume2,Fernandez Mikel2,Bernat Guillem3,Cazorla Francisco J.2

Affiliation:

1. Universitat Politècnica de Catalunya, Spain

2. Barcelona Supercomputing Center, Spain

3. Rapita Systems Ltd., UK

Funder

HiPEAC Network of Excellence

Ramon y Cajal postdoctoral fellowship

Juan de la Cierva-Formación postdoctoral fellowship

SuPerCom European Research Council (ERC) project under the European Union?s Horizon 2020 research and innovation programme

Juan de la-Cierva-Incorporacion postdoctoral fellowship

Spanish Ministry of Economy and Competitiveness (MINECO)

Publisher

ACM

Reference40 articles.

1. 2014. ARM Cortex-A53 MPCore Processor. http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500d/DDI0500D_cortex_a53_r0p2_trm.pdf 2014. ARM Cortex-A53 MPCore Processor. http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500d/DDI0500D_cortex_a53_r0p2_trm.pdf

2. 2018. CUDA Binary Utilities. https://docs.nvidia.com/pdf/CUDA_Binary_Utilities.pdf 2018. CUDA Binary Utilities. https://docs.nvidia.com/pdf/CUDA_Binary_Utilities.pdf

3. 2019. ARMv8 Reference Manual v8.5 EAC. https://static.docs.arm.com/ddi0487/ea/DDI0487E_a_armv8_arm.pdf 2019. ARMv8 Reference Manual v8.5 EAC. https://static.docs.arm.com/ddi0487/ea/DDI0487E_a_armv8_arm.pdf

4. Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain

5. T. Amert et al. 2017. GPU Scheduling on the NVIDIA TX2: Hidden Details Revealed. In RTSS. T. Amert et al. 2017. GPU Scheduling on the NVIDIA TX2: Hidden Details Revealed. In RTSS.

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