Affiliation:
1. Technische Universität Braunschweig, E.I.S., Braunschweig, Germany
Abstract
With the ever-increasing complexity of digital designs, debugging and evaluation face likewise increasing challenges. While recent advances in hardware/software co-simulation have been made, solutions for corresponding debugging and evaluation did not mature and improve in a similar fashion. In this article, we present a dedicated solution to ease the debugging and evaluation efforts, particularly focusing on full-system simulation. Improving significantly over existing solutions, the presented approach features a standards-compliant powerful and flexible method of deriving, logging, and filtering detailed status information from SystemC-based models. At the core of this approach are flexible scripting capabilities that may change all logging parameters during runtime, thus not requiring re-compiling the to-be-simulated model, as in many competing solutions. The approach is tested and benchmarked with a real-world full-system example, demonstrating the overall benefits. The presented solution is published as open source via github (see text) and, by strictly adhering to existing standards, is generally compatible with existing SystemC simulation environments.
Funder
German Federal Ministry of Education and Research
ARTEMIS Joint Undertaking
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Software
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