Enabling scalable chiplet-based uniform memory architectures with silicon photonics

Author:

Fotouhi Pouya1,Werner Sebastian1,Lowe-Power Jason1,Yoo S. J. Ben1

Affiliation:

1. University of California

Funder

National Science Foundation

U.S. Department of Defense

Publisher

ACM

Reference74 articles.

1. MCM-GPU

2. Noah Beck et al. 2018. 'Zeppelin': An SoC for multichip architectures. In ISSCC. IEEE. Noah Beck et al. 2018. 'Zeppelin': An SoC for multichip architectures. In ISSCC . IEEE.

3. Stéphane Bellenger et al. 2014. Silicon interposers with integrated passive devices: Ultra-miniaturized solution using 2.5 D packaging platform. Caen France IPDiA White Paper Silicon Interposers_260214 (2014). Stéphane Bellenger et al. 2014. Silicon interposers with integrated passive devices: Ultra-miniaturized solution using 2.5 D packaging platform. Caen France IPDiA White Paper Silicon Interposers_260214 (2014).

4. Keren Bergman et al. 2014. Photonic network-on-chip design. Springer. Keren Bergman et al. 2014. Photonic network-on-chip design . Springer.

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