Affiliation:
1. University of Kansas, Lawrence, KS, USA
2. Florida State University, Tallahassee, FL, USA
Abstract
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size, power, and cost-constrained domain of embedded systems. Different sequences of optimization phases have been observed to provide the best performance for different applications. Compiler writers and embedded systems developers have recently addressed this problem by conducting iterative empirical searches using machine-learning based heuristic algorithms in an attempt to find the phase sequences that are most effective for each application. Such searches are generally performed at the program level, although a few studies have been performed at the function level. The finer granularity of function-level searches has the potential to provide greater overall performance benefits, but only at the cost of slower searches caused by a greater number of performance evaluations that often require expensive program simulations. In this paper, we evaluate the performance benefits and search time increases of function-level approaches as compared to their program-level counterparts. We, then, present a novel search algorithm that conducts distinct function-level searches simultaneously, but requires only a single program simulation for evaluating the performance of potentially unique sequences for each function. Thus, our new hybrid search strategy provides the enhanced performance benefits of function-level searches with a search-time cost that is comparable to or less than program-level searches.
Publisher
Association for Computing Machinery (ACM)
Subject
Computer Graphics and Computer-Aided Design,Software
Cited by
11 articles.
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1. SRTuner: Effective Compiler Optimization Customization by Exposing Synergistic Relations;2022 IEEE/ACM International Symposium on Code Generation and Optimization (CGO);2022-04-02
2. A Survey on Compiler Autotuning using Machine Learning;ACM Computing Surveys;2019-09-30
3. A Study of Conflicting Pairs of Compiler Optimizations;2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2017-09
4. Piecewise holistic autotuning of parallel programs with CERE;Concurrency and Computation: Practice and Experience;2017-06-20
5. A graph-based iterative compiler pass selection and phase ordering approach;ACM SIGPLAN Notices;2016-08