Pushing ASIC performance in a power envelope

Author:

Puri Ruchir,Stok Leon,Cohn John,Kung David,Pan David,Sylvester Dennis,Srivastava Ashish,Kulkarni Sarvesh

Publisher

ACM Press

Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction;2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD);2023-09-10

2. Energy-efficient CMOS voltage level shifters with single-$$\hbox {V}_{{DD}}$$ for multi-core applications;Analog Integrated Circuits and Signal Processing;2021-01-01

3. Wide-range energy-efficient buffer-based voltage level-up converters for multi-supply voltage systems;Sādhanā;2020-11-03

4. Body Built-In Cells for Detecting Transient Faults and Adaptively Biasing Subcircuits;On-Chip Current Sensors for Reliable, Secure, and Low-Power Integrated Circuits;2019-10-01

5. Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI;VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things;2019

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