Efficient Memory Partitioning for Parallel Data Access via Data Reuse-Reference-Cited by-同舟云学术

Efficient Memory Partitioning for Parallel Data Access via Data Reuse

Published:2016-02-21 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
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Author:

Su Jincheng¹,Yang Fan¹,Zeng Xuan¹,Zhou Dian²

Affiliation:

1. Fudan University, Shanghai, China

2. University of Texas at Dallas, Dallas, TX, USA

Funder

Chen Guang project supported by Shanghai Municipal Education Commission and Shanghai Education Development Foundation

Recruitment Program of Global Experts (the Thousand Talents Plan)

NSF

National Natural Science Foundation of China

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2847263.2847264

Reference19 articles.

1. M. Fingeroff High-level synthesis blue book. 2010. M. Fingeroff High-level synthesis blue book. 2010.

2. D. T. W. Bruce Jacob Spencer W. Ng Memory Systems -- Cache DRAM Disk. Denise E.M. Penrose 2008. D. T. W. Bruce Jacob Spencer W. Ng Memory Systems -- Cache DRAM Disk. Denise E.M. Penrose 2008.

3. Fast quadratic increase of multiport-storage-cell area with port number

4. Y. B. Asher and N. Rotem "Automatic memory partitioning: increasing memory parallelism via data structure partitioning " in Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis 2010 pp. 155--162. 10.1145/1878961.1878989 Y. B. Asher and N. Rotem "Automatic memory partitioning: increasing memory parallelism via data structure partitioning " in Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis 2010 pp. 155--162. 10.1145/1878961.1878989

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