Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis-Reference-Cited by-同舟云学术

Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis

Published:2016-02-21 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
language:
Short-container-title:

Author:

Gao Xitong¹,Wickerson John¹,Constantinides George A.¹

Affiliation:

1. Imperial College London, London, United Kingdom

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2847263.2847282

Reference26 articles.

1. An overview of today’s high-level synthesis tools

2. Berkeley Design Technology Inc. "An Independent Evaluation of: High-Level Synthesis Tools for Xilinx FPGAs " 2010. {Online}. Available: http://www.xilinx.com/technology/dsp/BDTI_techpaper.pdf Berkeley Design Technology Inc. "An Independent Evaluation of: High-Level Synthesis Tools for Xilinx FPGAs " 2010. {Online}. Available: http://www.xilinx.com/technology/dsp/BDTI_techpaper.pdf

3. A. Canis S. D. Brown and J. H. Anderson "Modulo SDC scheduling with recurrence minimization in high-level synthesis " in FPL 2014. A. Canis S. D. Brown and J. H. Anderson "Modulo SDC scheduling with recurrence minimization in high-level synthesis " in FPL 2014.

4. N. J. Higham Accuracy and Stability of Numerical Algorithms 2nd ed. Philadelphia PA USA: Society for Industrial and Applied Mathematics 2002. N. J. Higham Accuracy and Stability of Numerical Algorithms 2nd ed. Philadelphia PA USA: Society for Industrial and Applied Mathematics 2002.

5. Xilinx Inc. "Vivado Design Suite User Guide--High-Level Synthesis " 2015. Xilinx Inc. "Vivado Design Suite User Guide--High-Level Synthesis " 2015.

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Review of Spatial Exploration of FPGA Design;Computer Science and Application;2022

2. Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis;IEEE Transactions on Computers;2021-12-01

3. Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration;2021 IEEE International Workshop on Rapid System Prototyping (RSP);2021-10-14

4. Automatic Selection and Insertion of HLS Directives Via a Source-to-Source Compiler;2020 International Conference on Field-Programmable Technology (ICFPT);2020-12

5. Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-07