Scalability Limitations of Processing-in-Memory using Real System Evaluations

Author:

Jonatan Gilbert1ORCID,Cho Haeyoon1ORCID,Son Hyojun1ORCID,Wu Xiangyu1ORCID,Livesay Neal2ORCID,Mora Evelio3ORCID,Shivdikar Kaustubh2ORCID,Abellán José L.4ORCID,Joshi Ajay5ORCID,Kaeli David2ORCID,Kim John1ORCID

Affiliation:

1. KAIST, Daejeon, Republic of Korea

2. Northeastern University, Boston, USA

3. Universidad Católica de Murcia, Murcia, Spain

4. Universidad de Murcia, Murcia, Spain

5. Boston University, Boston, USA

Abstract

Processing-in-memory (PIM), where the compute is moved closer to the memory or the data, has been widely explored to accelerate emerging workloads. Recently, different PIM-based systems have been announced by memory vendors to minimize data movement and improve performance as well as energy efficiency. One critical component of PIM is the large amount of compute parallelism provided across many PIM "nodes'' or the compute units near the memory. In this work, we provide an extensive evaluation and analysis of real PIM systems based on UPMEM PIM. We show that while there are benefits of PIM, there are also scalability challenges and limitations as the number of PIM nodes increases. In particular, we show how collective communications that are commonly found in many kernels/workloads can be problematic for PIM systems. To evaluate the impact of collective communication in PIM architectures, we provide an in-depth analysis of two workloads on the UPMEM PIM system that utilize representative common collective communication patterns -- AllReduce and All-to-All communication. Specifically, we evaluate 1) embedding tables that are commonly used in recommendation systems that require AllReduce and 2) the Number Theoretic Transform (NTT) kernel which is a critical component of Fully Homomorphic Encryption (FHE) that requires All-to-All communication. We analyze the performance benefits of these workloads and show how they can be efficiently mapped to the PIM architecture through alternative data partitioning. However, since each PIM compute unit can only access its local memory, when communication is necessary between PIM nodes (or remote data is needed), communication between the compute units must be done through the host CPU, thereby severely hampering application performance. To increase the scalability (or applicability) of PIM to future workloads, we make the case for how future PIM architectures need efficient communication or interconnection networks between the PIM nodes that require both hardware and software support.

Publisher

Association for Computing Machinery (ACM)

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

2. SwiftRL: Towards Efficient Reinforcement Learning on Real Processing-In-Memory Systems;2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2024-05-05

3. NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3;2024-04-27

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