Formal verification of phase-locked loops using reachability analysis and continuization

Author:

Althoff Matthias1,Rajhans Akshay2,Krogh Bruce H.2,Yaldiz Soner3,Li Xin2,Pileggi Larry2

Affiliation:

1. Ilmenau University of Technology, Ilmenau, Germany

2. Carnegie Mellon University, Pittsburgh, PA

3. Intel Corporation, Hillsboro, OR

Abstract

We present a scalable and formal technique to verify locking time and stability for charge-pump phase-locked loops (PLLs). In contrast to the traditional simulation approach that only validates the PLL at a given operation condition, our proposed technique formally verified the PLL at all possible operation conditions. The dynamics of the PLL is described by a hybrid automaton, which incorporates the differential equations of the analog circuit elements as well as the switching logic of the digital circuit elements. Existing methods for computing reachable sets for hybrid automata cannot be used to verify the PLL model due to the large number of cycles required for locking. We develop a new method for computing effective overapproximations of the sets of states reached on each cycle by using uncertain parameters in a discrete-time model to represent the range of possible switching times, a technique we call continuization . Using this new method for reachability analysis, it is possible to verify locking specifications for a charge-pump PLL design for all possible initial states and parameter values in time comparable to the time required for a few simulation runs of the same behavioral model.

Funder

Division of Computing and Communication Foundations

C2S2 Focus Center

Publisher

Association for Computing Machinery (ACM)

Subject

General Computer Science

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