DRAM-related challenges in task scheduling with timing predictability on COTS multi-cores for safety-critical systems
Author:
Affiliation:
1. Technische Universität Kaiserslautern, Kaiserslautern, Germany
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3132402.3132417
Reference11 articles.
1. Sven Goossens Karthik Chandrasekar Benny Akesson and Kees Goossens. 2016. Memory Controllers for Mixed-Time-Criticality Systems. Springer International Publishing. Sven Goossens Karthik Chandrasekar Benny Akesson and Kees Goossens. 2016. Memory Controllers for Mixed-Time-Criticality Systems. Springer International Publishing.
2. The Multi-Resource Server for predictable execution on multi-core platforms
3. Bounding memory interference delay in COTS-based multi-core systems
4. Leveraging Multi-core Computing Architectures in Avionics
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