Affiliation:
1. Ghent University, Belgium, Gent, Belgium
Abstract
Compilers for Course-Grained Reconfigurable Array (CGRA) architectures suffer from long compilation times and code quality levels far below the theoretical upper bounds. This article presents a new scheduler, called the Bimodal Modulo Scheduler (BMS), to map inner loops onto (heterogeneous) CGRAs of the Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) family. BMS significantly outperforms existing schedulers for similar architectures in terms of generated code quality and compilation time. This is achieved by combining new schemes for backtracking with extended and adapted forms of priority functions and cost functions, as described in the article. BMS is evaluated by mapping multimedia and software-defined radio benchmarks onto tuned ADRES instances.
Funder
Agency for Innovation by Science and Technology in Flanders, Belgium
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Information Systems,Software
Cited by
9 articles.
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1. CaSMap;Proceedings of the 49th Annual International Symposium on Computer Architecture;2022-06-11
2. PathSeeker: A Fast Mapping Algorithm for CGRAs;2022 Design, Automation & Test in Europe Conference & Exhibition (DATE);2022-03-14
3. Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA;Electronics;2021-09-09
4. Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling;IEEE Transactions on Parallel and Distributed Systems;2020-09-01
5. Coarse-Grained Reconfigurable Array Architectures;Handbook of Signal Processing Systems;2018-10-14