A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design
Author:
Affiliation:
1. UFRGS, Porto Alegre, Brazil
2. PPGC, UFRGS, Brazil
Funder
FAPERGS
CNPq
CAPES
European Community's Seventh Frame-work Programme
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2717764.2717785
Reference44 articles.
1. The future of interconnection technology
2. The future of logic synthesis and physical design in deep-submicron process geometries
3. Wireplanning in logic synthesis
4. Safe Delay Optimization for Physical Synthesis
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