Affiliation:
1. University of Twente, Enschede, Netherlands
2. National Tsing Hua University, Hsinchu, Taiwan
3. Technical University of Dortmund, Dortmund, Germany
Abstract
For timing-sensitive edge applications, the demand for efficient lightweight machine learning solutions has increased recently. Tree ensembles are among the state-of-the-art in many machine learning applications. While single decision trees are comparably small, an ensemble of trees can have a significant memory footprint leading to cache locality issues, which are crucial to performance in terms of execution time. In this work, we analyze memory-locality issues of the two most common realizations of decision trees, i.e., native and if-else trees. We highlight that both realizations demand a more careful memory layout to improve caching behavior and maximize performance. We adopt a probabilistic model of decision tree inference to find the best memory layout for each tree at the application layer. Further, we present an efficient heuristic to take architecture-dependent information into account thereby optimizing the given ensemble for a target computer architecture. Our code-generation framework, which is freely available on an open-source repository, produces optimized code sessions while preserving the structure and accuracy of the trees. With several real-world data sets, we evaluate the elapsed time of various tree realizations on server hardware as well as embedded systems for Intel and ARM processors. Our optimized memory layout achieves a reduction in execution time up to 75 % execution for server-class systems, and up to 70 % for embedded systems, respectively.
Funder
Federal Ministry of Education and Research of Germany as part of the competence center for machine learning ML2R
Deutsche Forschungsgemeinschaft
Deutscher Akademischer Austauschdienst (DAAD) within the Programme for Project-Related Personal Exchange
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Software
Cited by
13 articles.
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