DHOOM
Author:
Affiliation:
1. IIT Delhi
2. IIT Palakkad
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3316781.3317799
Reference18 articles.
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2. A. Basak S. Bhunia and S. Ray. 2016. Exploiting design-for-debug for flexible SoC security architecture. In DAC. ACM. 10.1145/2897937.2898020 A. Basak S. Bhunia and S. Ray. 2016. Exploiting design-for-debug for flexible SoC security architecture. In DAC. ACM. 10.1145/2897937.2898020
3. S. Chandran P. R. Panda S. R. Sarangi A. Bhattacharyya D. Chauhan and S. Kumar. 2017. Managing Trace Summaries to Minimize Stalls During Postsilicon Validation. IEEE TVLSI 25 6 (2017). S. Chandran P. R. Panda S. R. Sarangi A. Bhattacharyya D. Chauhan and S. Kumar. 2017. Managing Trace Summaries to Minimize Stalls During Postsilicon Validation. IEEE TVLSI 25 6 (2017).
4. N. Decker P. Gottschling C. Hochberger M. Leucker T. Scheffel M. Schmitz and A. Weiss. 2017. Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems. In SBMF. Springer. N. Decker P. Gottschling C. Hochberger M. Leucker T. Scheffel M. Schmitz and A. Weiss. 2017. Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems. In SBMF. Springer.
5. D. Y Deng D. Lo G. Malysa S. Schneider and G E. Suh. 2010. Flexible and efficient instruction-grained run-time monitoring using on-chip reconfigurable fabric. In MICRO. IEEE. 10.1109/MICRO.2010.17 D. Y Deng D. Lo G. Malysa S. Schneider and G E. Suh. 2010. Flexible and efficient instruction-grained run-time monitoring using on-chip reconfigurable fabric. In MICRO. IEEE. 10.1109/MICRO.2010.17
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1. A Formal Approach to Accountability in Heterogeneous Systems-on-Chip;IEEE Transactions on Dependable and Secure Computing;2021-11-01
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