1. BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. Two-layer Bottleneck Channel Track Assignment for Analog VLSI;IPSJ Transactions on System and LSI Design Methodology;2024
3. Detailed Routing;VLSI Physical Design: From Graph Partitioning to Timing Closure;2022
4. Routability-aware pin access optimization for monolithic 3D designs;Proceedings of the 39th International Conference on Computer-Aided Design;2020-11-02
5. Hardness of crosstalk minimization in two-layer channel routing;Integration;2017-01