Automated Lithography Resolution Enhancement with Deep Learning Enabled Layout Modification during Physical Design Stage

Author:

Liu Zixi1ORCID,Lin Yibo2ORCID,Su Xiaojing3ORCID,Ling Xiaohuan3ORCID,Hong Xin4ORCID,Ma Bojie3ORCID,Su Yajuan3ORCID,Wei Yayi3ORCID

Affiliation:

1. EDA Center, Institute of Microelectronics of the Chinese Academy of Sciences, China

2. Peking University, China

3. Institute of Microelectronics of the Chinese Academy of Sciences, China

4. Institute of Microelectronics of The Chinese Academy of Science, Institute of Microelectronics of the Chinese Academy of Sciences, China

Funder

Advanced Major Project of Chinese Academy of Sciences

Youth Innovation Promotion Association Chinese Academy of Sciences

Chinese Ministry of Science and Technology

Guangdong Province Research and Development Program in Key Fields

National Natural Science Foundation of China

Publisher

ACM

Reference16 articles.

1. [1] Chris Spence. Full-chip lithography simulation and design analysis: how opc is changing ic design. In Emerging Lithographic Technologies IX, volume 5751, pages 1–14. SPIE, 2005.

2. How to make lithography patterns print: the role of OPC and pattern layout

3. Mask optimization approaches in optical lithography based on a vector imaging model

4. [4] Yayi Wei and Robert L Brainard. Advanced processes for 193-nm immersion lithography, volume 189. Proceedings of SPIE, 2009.

5. [5] Xu Wang, Wei Shi, Michael Hochberg, Kostas Adam, Ellen Schelew, Jeff F Young, Nicolas AF Jaeger, and Lukas Chrostowski. Lithography simulation for the fabrication of silicon photonic devices with deep-ultraviolet lithography. In The 9th International Conference on Group IV Photonics (GFP), pages 288–290. IEEE, 2012.

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