MIA-Aware Detailed Placement and VT Reassignment for Leakage Power Optimization

Author:

Lin Hung-Chun1,Fang Shao-Yun1

Affiliation:

1. National Taiwan University of Science and Technology, Taipei, Taiwan

Funder

National Science and Technology Council

Publisher

ACM

Reference13 articles.

1. IBM ILOG CPLEX Optimizer. http://www-01.ibm.com/software/integration/optimization/cplex-optimizer/ IBM ILOG CPLEX Optimizer. http://www-01.ibm.com/software/integration/optimization/cplex-optimizer/

2. A. B. Kahng and H. Lee , " Minimum implant area-aware gate sizing and placement," in Proceedings of the Great Lakes Symposium on VLSI , 2014 . A. B. Kahng and H. Lee, "Minimum implant area-aware gate sizing and placement," in Proceedings of the Great Lakes Symposium on VLSI, 2014.

3. Minimum Implant Area-Aware Placement and Threshold Voltage Refinement

4. K.-H. Tseng Y.-W. Chang and C.-C. Liu "Minimum-implant-area-aware detailed placement with spacing constraints " In Proceedings of Design Automation Conference 2016. K.-H. Tseng Y.-W. Chang and C.-C. Liu "Minimum-implant-area-aware detailed placement with spacing constraints " In Proceedings of Design Automation Conference 2016.

5. Mixed-cell-height detailed placement considering complex minimum-implant-area constraints;Wu Y.-Y.;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2021

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2. Improved Self-Biased Differential Amplifiers Using Multiple-Vt CMOS Transistors;2023 7th International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT);2023-08-28

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