Author:
Singh Deshanand P.,Brown Stephen D.
Cited by
16 articles.
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1. RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm;ACM Transactions on Reconfigurable Technology and Systems;2022-06-06
2. The Stratix™ 10 Highly Pipelined FPGA Architecture;Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2016-02-21
3. Using C-Slow Retiming in Safety Critical and Low Power Applications;FPGAs and Parallel Architectures for Aerospace Applications;2016
4. A Bio-Inspired Technique for Energy-Aware FPGAs on Body Area Networks;IEEE Latin America Transactions;2015-12
5. A Timing Error Mitigation Technique for High Performance Designs;2015 IEEE Computer Society Annual Symposium on VLSI;2015-07