Affiliation:
1. Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Abstract
Pipeline stalls due to conditional branches represent one of the most significant impediments to realizing the performance potential of deeply pipelined, superscalar processors. Many branch predictors have been proposed to help alleviate this problem, including the Two-Level Adaptive Branch Predictor, and more recently, two-component hybrid branch predictors.In a less idealized environment, such as a time-shared system, code of interest involves context switches. Context switches, even at fairly large intervals, can seriously degrade the performance of many of the most accurate branch prediction schemes. In this paper, we introduce a new hybrid branch predictor and show that it is more accurate (for a given cost) than any previously published scheme, especially if the branch histories are periodically flushed due to the presence of context switches.
Publisher
Association for Computing Machinery (ACM)
Cited by
31 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Enhancing Microarchitecture Performance through Synergistic Dynamic Branch Prediction and Cache Prefetching;2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom);2023-12-07
2. MBPlib: Modular Branch Prediction Library;2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2023-04
3. Research on Security Technology of Processor Branch Prediction;2022 International Conference on Computing, Communication, Perception and Quantum Technology (CCPQT);2022-08
4. STBPU: A Reasonably Secure Branch Prediction Unit;2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN);2022-06
5. HyBP: Hybrid Isolation-Randomization Secure Branch Predictor;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04