Parameterized loop tiling
Author:
Affiliation:
1. IBM T.J. Watson Research Center, Yorktown Heights, NY
2. CORESPEQ, Inc., Milpitas, CA
3. Colorado State University, Fort Collins, CO
Abstract
Publisher
Association for Computing Machinery (ACM)
Subject
Software
Link
https://dl.acm.org/doi/pdf/10.1145/2160910.2160912
Reference43 articles.
1. Amarasinghe S. 1997. Parallelizing compiler techniques based on linear inequalities. Ph.D. thesis Stanford University. Amarasinghe S. 1997. Parallelizing compiler techniques based on linear inequalities. Ph.D. thesis Stanford University.
2. Communication optimization and code generation for distributed memory machines
3. Scanning polyhedra with DO loops
4. Optimal Orthogonal Tiling of 2-D Iterations
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