Affiliation:
1. Brunel University London, UK
2. DePaul University, USA
Abstract
The integration of transactions into hardware relaxed memory architectures is a topic of current research both in industry and academia. In this paper, we provide a general architectural framework for the introduction of transactions into models of relaxed memory in hardware, including the SC, TSO, ARMv8 and PPC models. Our framework incorporates flexible and expressive forms of transaction aborts and execution that have hitherto been in the realm of software transactional memory. In contrast to software transactional memory, we account for the characteristics of relaxed memory as a restricted form of distributed system, without a notion of global time. We prove abstraction theorems to demonstrate that the programmer API matches the intuitions and expectations about transactions.
Publisher
Association for Computing Machinery (ACM)
Subject
Safety, Risk, Reliability and Quality,Software
Cited by
9 articles.
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2. Finding Memory Bound of Cloned Objects in Software Transactional Memory Programs;International Journal of Software Engineering and Knowledge Engineering;2022-06
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4. The Code That Never Ran: Modeling Attacks on Speculative Evaluation;2019 IEEE Symposium on Security and Privacy (SP);2019-05
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