Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems-Reference-Cited by-同舟云学术

Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems

Published:2016-10 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
language:
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Author:

Xie Mimi¹,Zhao Mengying²,Pan Chen¹,Li Hehe³,Liu Yongpan³,Zhang Youtao⁴,Xue Chun Jason⁵,Hu Jingtong¹

Affiliation:

1. Oklahoma State University

2. Shandong University, China

3. Tsinghua University, China

4. University of Pittsburgh

5. City University of Hong Kong, Hong Kong

Funder

Research Grants Council of the Hong Kong Special Administrative Region, China

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2968456.2968477

Reference39 articles.

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2. The gem5 simulator

3. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

4. J. L. Henning. Spec cpu2006 benchmark descriptions. ACM SIGARCH Computer Architecture News 34(4):1--17 2006. 10.1145/1186736.1186737 J. L. Henning. Spec cpu2006 benchmark descriptions. ACM SIGARCH Computer Architecture News 34(4):1--17 2006. 10.1145/1186736.1186737

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