IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design Stages

Abstract

The detail routing process is by far the most time consuming during the physical design flow. Routing starts with an estimation of timing slacks and aims to meet the timing specifications at signoff. In this paper, we propose an improved method to predict the net delays using RandomForestRegressor and thereby predict critical paths early on at placement stage. Quick timing prediction is also essential in making time-sensitive edits to stepping of the chip based on post-Si feedback. The proposed algorithm is based on five novel features, namely, targeted feature selection, introduction of a one-hot encoding scheme, an outlier identification method, post-route buffer-bloat prediction and post-route cell sizing prediction. Experimental results on academic benchmarks and industry circuits, both on advanced 10nm process node show that the proposed algorithm has led to significant improvements in accurately predicting timing slacks when compared with state of the art. The proposed algorithm predicts slack within 0.598% of signoff results, whereas the state of art results are erroneous by an average of 53.33% for the same metric. Overall time savings of 44.1% is seen when compared to running the traditional flow, and savings of 90% seen for obtaining the timing results.