Affiliation:
1. Digital Equipment Corporation, Hudson, MA
Abstract
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that write to the same memory location. One approach is to use memory dependence prediction to identify the stores upon which a load depends, and communicate that information to the instruction scheduler. We designate the set of stores upon which each load has depended as the load's "store set". The processor can discover and use a load's store set to accurately predict the earliest time the load can safely execute. We show that store sets accurately predict memory dependencies in the context of large instruction window, superscalar machines, and allow for near-optimal performance compared to an instruction scheduler with perfect knowledge of memory dependencies. In addition, we explore the implementation aspects of store sets, and describe a low cost implementation that achieves nearly optimal performance.
Publisher
Association for Computing Machinery (ACM)
Reference12 articles.
1. K. Ycagcr. The MIPS R10000 Supcrscalar Microprocessor. Hot Chips VII 1995. K. Ycagcr. The MIPS R10000 Supcrscalar Microprocessor. Hot Chips VII 1995.
2. Intel Corporation. Pentium(R) Pro Developer's Manual. McGraw-Hill June 1997. Intel Corporation. Pentium(R) Pro Developer's Manual. McGraw-Hill June 1997.
3. Dynamic speculation and synchronization of data dependences
Cited by
19 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29
2. Improving Memory Dependence Prediction with Static Analysis;Lecture Notes in Computer Science;2024
3. Study of Microprocessor-Based Control Devices;International Journal of Scientific Research in Science and Technology;2023-01-01
4. Efficient Instruction Scheduling Using Real-time Load Delay Tracking;ACM Transactions on Computer Systems;2022-11-24
5. ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading;MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture;2021-10-17