Enabling high-level parallel programming on multi-FPGA clusters

Author:

de Haro Ruiz Juan Miguel1ORCID,Ávarez Martínez Carlos1ORCID,Jiménez-González Daniel1ORCID,Martorell Bofill Xavier1ORCID

Affiliation:

1. Computer Sciences, Barcelona Supercomputing Center, Spain and Computer Architecture, Universitat Politècnica de Catalunya, Spain

Publisher

ACM

Reference28 articles.

1. AMD 2024. UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203). AMD. https://docs.amd.com/r/en-US/pg203-cmac-usplus/UltraScale-Devices-Integrated-100G-Ethernet-Subsystem-v3.1-LogiCORE-IP-Product-Guide.

2. Roberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Andrea Ciardiello, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, 2023. APEIRON: a Framework for High Level Programming of Dataflow Applications on Multi-FPGA Systems. In 26TH International Conference on Computing in High Energy & Nuclear Physics (CHEP 2023).

3. blas 2024. Basic Linear Algebra Subprograms. Retrieved March 26, 2024 from https://www.netlib.org/blas

4. The Future of FPGA Acceleration in Datacenters and the Cloud

5. Ethernet Emulation over PCIe for RISC-V Software Development Vehicles

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