1. Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
2. BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework
3. Eric Brochu, Vlad M. Cora, and Nando de Freitas. 2010. A Tutorial on Bayesian Optimization of Expensive Cost Functions, with Application to Active User Modeling and Hierarchical Reinforcement Learning. CoRR abs/1012.2599 (2010), 49 pages. arXiv:1012.2599http://arxiv.org/abs/1012.2599
4. Chips Alliance. 2024. Cores-VeeR-EL2: A RISC-V Core. https://github.com/chipsalliance/Cores-VeeR-EL2. Available online: https://github.com/chipsalliance/Cores-VeeR-EL2.
5. Jose GF Coutinho, Ce Guo, Tim Todman, and Wayne Luk. 2023. Exploring Machine Learning Adoption in Customisable Processor Design. In 2023 IEEE 15th International Conference on ASIC (ASICON). IEEE, Nanjing, China, 1–4.