Temporal Logic Formalisation of ISO 34502 Critical Scenarios: Modular Construction with the RSS Safety Distance

Author:

Reimann Jesse1ORCID,Mansion Nico2ORCID,Haydon James3ORCID,Bray Benjamin3ORCID,Chattopadhyay Agnishom4ORCID,Sato Sota5ORCID,Waga Masaki6ORCID,André Étienne7ORCID,Hasuo Ichiro5ORCID,Ueda Naoki8ORCID,Yokoyama Yosuke8ORCID

Affiliation:

1. TU Delft, Delft, Netherlands

2. Saarland University, Saarbrücken, Germany

3. National Institute of Informatics, Tokyo, Japan

4. Rice University, Houston, Texas, USA

5. NII & SOKENDAI, Tokyo, Japan

6. Kyoto University & NII, Kyoto, Japan

7. Université Sorbonne Paris Nord, Paris, France

8. Mitsubishi Electric Corporation, Kamakura, Japan

Funder

Japan Science and Technology Agency

Publisher

ACM

Reference33 articles.

1. Y. Annpureddy, C. Liu, G. Fainekos, and S. Sankaranarayanan. 2011. S-TaLiRo: A Tool for Temporal Logic Falsification for Hybrid Systems. In TACAS 2011, Vol. 6605. Springer, 254--257.

2. C.Baier and J.-P. Katoen. 2008. Principles of Model Checking. The MIT Press.

3. P. Bender, J. Ziegler, and C. Stiller. 2014. Lanelets: Efficient map representation for autonomous driving. In IV 2014. 420--425.

4. STL⁎: Extending signal temporal logic with signal-value freezing operator

5. A. Donzé. 2010. Breach, A Toolbox for Verification and Parameter Synthesis of Hybrid Systems. In CAV 2010, Vol. 6174. Springer, 167--170.

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