Affiliation:
1. University of Michigan, Ann Arbor, MI
Abstract
This paper proposes new network interface controller (NIC) designs that take advantage of integration with the host CPU to provide increased flexibility for operating system kernel-based performance optimization.We believe that this approach is more likely to meet the needs of current and future high-bandwidth TCP/IP networking on end hosts than the current trend of putting more complexity in the NIC, while avoiding the need to modify applications and protocols. This paper presents two such NICs. The first, the simple integrated NIC (SINIC), is a minimally complex design that moves the responsibility for managing the network FIFOs from the NIC to the kernel. Despite this closer interaction between the kernel and the NIC, SINIC provides performance equivalent to a conventional DMA-based NIC without increasing CPU overhead. The second design, V-SINIC, adds virtual per-packet registers to SINIC, enabling parallel packet processing while maintaining a FIFO model. V-SINIC allows the kernel to decouple examining a packet's header from copying its payload to memory. We exploit this capability to implement a true zero-copy receive optimization in the Linux 2.6 kernel, providing bandwidth improvements of over 50% on unmodified sockets-based receive-intensive benchmarks.
Publisher
Association for Computing Machinery (ACM)
Reference39 articles.
1. Alacritech Inc. Alacritech / SLIC technology overview. http://www.alacritech.com/html/tech review.html. Alacritech Inc. Alacritech / SLIC technology overview. http://www.alacritech.com/html/tech review.html.
2. Apache Software Foundation. Apache HTTP server. http://httpd.apache.org. Apache Software Foundation. Apache HTTP server. http://httpd.apache.org.
3. Generating representative Web workloads for network and server performance evaluation
4. The M5 Simulator: Modeling Networked Systems
5. Performance analysis of system overheads in TCP/IP workloads
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