Low-power, low-storage-overhead chipkill correct via multi-line error correction-Reference-Cited by-同舟云学术

Low-power, low-storage-overhead chipkill correct via multi-line error correction

Published:2013-11-17 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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Author:

Jian Xun¹,Duwe Henry¹,Sartori John²,Sridharan Vilas³,Kumar Rakesh¹

Affiliation:

1. University of Illinois at Urbana-Champaign

2. University of Minnesota

3. Advanced Micro Devices, Inc.

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2503210.2503243

Reference26 articles.

1. "AMD BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors " 2007. {Online}. Available: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf "AMD BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors " 2007. {Online}. Available: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf

2. "CACTI 5.3 " 2008. {Online}. Available: http://quid.hpl.hp.com:9081/cacti "CACTI 5.3 " 2008. {Online}. Available: http://quid.hpl.hp.com:9081/cacti

3. Future scaling of processor-memory interfaces

4. C. Bienia "Benchmarking Modern Multiprocessors " Ph.D. dissertation Princeton NJ USA 2011. C. Bienia "Benchmarking Modern Multiprocessors " Ph.D. dissertation Princeton NJ USA 2011.

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