Tera-scale 1D FFT with low-communication algorithm and Intel® Xeon Phi™ coprocessors

Author:

Park Jongsoo1,Bikshandi Ganesh1,Vaidyanathan Karthikeyan1,Tang Ping Tak Peter2,Dubey Pradeep1,Kim Daehyun1

Affiliation:

1. Parallel Computing Lab

2. Software and Service Group, Intel Corporation

Publisher

ACM

Reference33 articles.

1. Intel® Xeon Phi#8482; Coprocessor Instruction Set Architecture Reference Manual. Intel® Xeon Phi#8482; Coprocessor Instruction Set Architecture Reference Manual.

2. HPC Challenge Benchmark Results. http://icl.cs.utk.edu/hpcc/hpcc_results.cgi. HPC Challenge Benchmark Results. http://icl.cs.utk.edu/hpcc/hpcc_results.cgi.

3. RIKEN Next-Generation Supercomputer R&D Center. http://www.nsc.riken.jp/index-eng.html. RIKEN Next-Generation Supercomputer R&D Center. http://www.nsc.riken.jp/index-eng.html.

4. The Tofu Interconnect

5. FFTs in external or hierarchical memory

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