High-performance raster graphics for microcomputer systems

Author:

Bechtolsheim Andreas1,Baskett Forest1

Affiliation:

1. Computer Systems Laboratory, Stanford University, Stanford, California

Abstract

A frame buffer architecture is presented that reduces the overhead of frame buffer updating by three means. First, the bit-map memory is (x,y) addressable, whereby a string of pixels can be accessed in parallel. Second, the pixel-change operation is performed by hardware in a single read-modify-write cycle. Third, multiple objects in the frame buffer are addressable simultaneously by a set of address registers. The remaining task of generating (x,y) addresses and providing new data can be managed rapidly by current microprocessors or DMA-devices. With a modest expenditure of hardware, this architecture eliminates all the bit-shifting, bit-masking, and bit-manipulation conventionally associated with frame buffer graphics, while retaining the full generality of user-programmable control. The particular implementation described allows raster manipulation at full bit-map memory bandwidth. It can paint a 16×16 pixel character into the frame buffer in 16 microseconds and can modify a 1024×1024 pixel raster in 64 milliseconds.

Publisher

Association for Computing Machinery (ACM)

Subject

Computer Graphics and Computer-Aided Design,General Computer Science

Reference3 articles.

1. I.E. Sutherland R.F. Sproull S. Gupta A. Thompson personal communication. I.E. Sutherland R.F. Sproull S. Gupta A. Thompson personal communication.

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