Exploring emerging CNFET for efficient last level cache design-Reference-Cited by-同舟云学术

Exploring emerging CNFET for efficient last level cache design

Published:2019-01-21 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 24th Asia and South Pacific Design Automation Conference
language:
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Author:

Xu Dawen¹,Li Li¹,Wang Ying²,Liu Cheng²,Li Huawei²

Affiliation:

1. Institute of Computing Technology Chinese Academy of Science, Beijing, China and School of Electronic Science & Applied Physics Hefei University of Technology Anhui, China

2. Institute of Computing Technology Chinese Academy of Science, Beijing, China

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3287624.3287700

Reference20 articles.

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2. DeepBurning

3. A survey on cache tuning from a power/energy perspective

4. Digital VLSI logic technology using Carbon Nanotube FETs

5. Carbon nanotube circuits in the presence of carbon nanotube density variations

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1. Taming Process Variations in CNFET for Efficient Last-Level Cache Design;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021

2. Carbon Nanotube Length Variation in Correlated CNFETs;2020 IEEE 20th International Conference on Nanotechnology (IEEE-NANO);2020-07