BeSAT
Author:
Affiliation:
1. Northwestern University
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3287624.3287670
Reference21 articles.
1. Integrated circuit security
2. A. Baumgarten A. Tyagi and J. Zambreno. Preventing ic piracy using reconfigurable logic barriers. IEEE Design and Test 27(1) 2010. 10.1109/MDT.2010.24 A. Baumgarten A. Tyagi and J. Zambreno. Preventing ic piracy using reconfigurable logic barriers. IEEE Design and Test 27(1) 2010. 10.1109/MDT.2010.24
3. R. Chen and H. Zhou. Statistical timing verification for transparently latched circuits. IEEE TCAD 25(9) 2006. 10.1109/TCAD.2005.857395 R. Chen and H. Zhou. Statistical timing verification for transparently latched circuits. IEEE TCAD 25(9) 2006. 10.1109/TCAD.2005.857395
4. A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans
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