Affiliation:
1. Computer Systems Laboratory, Stanford University, Stanford, CA
2. Department of Computer Science, Princeton University, Princeton, NJ
Abstract
The SPLASH-2 suite of parallel applications has recently been released to facilitate the study of centralized and distributed shared-address-space multiprocessors. In this context, this paper has two goals. One is to quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well. The properties we study include the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality, as well as how these properties scale with problem size and the number of processors. The other, related goal is methodological: to assist people who will use the programs in architectural evaluations to prune the space of application and machine parameters in an informed and meaningful way. For example, by characterizing the working sets of the applications, we describe which operating points in terms of cache size and problem size are representative of realistic situations, which are not, and which re redundant. Using SPLASH-2 as an example, we hope to convey the importance of understanding the interplay of problem size, number of processors, and working sets in designing experiments and interpreting their results.
Publisher
Association for Computing Machinery (ACM)
Cited by
276 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. KLNK: Expanding Page Boundaries in a Distributed Shared Memory System;IEEE Transactions on Parallel and Distributed Systems;2024-09
2. HQ-DTM: A Hierarchical Q-learning Algorithm for Dynamic Thermal Management of Multi-core Processors;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05
3. OpSAVE: Eviction Based Scheme for Efficient Optical Network-on-Chip;Microprocessors and Microsystems;2024-07
4. Design of an efficient hybrid cache coherence protocol on chiplet architecture;Third International Conference on Algorithms, Microchips, and Network Applications (AMNA 2024);2024-06-08
5. Decntr: Optimizing Safety and Schedulability with Multi-Mode Control and Resource Allocation Co-Design;2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS);2024-05-13