The MIT Alewife machine

Author:

Agarwal Anant1,Bianchini Ricardo2,Chaiken David3,Johnson Kirk L.1,Kranz David1,Kubiatowicz John1,Lim Beng-Hong4,Mackenzie Kenneth1,Yeung Donald1

Affiliation:

1. Laboratory for Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts

2. University of Rochester, Rochester, NY and Laboratory for Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts

3. Digital Equipment Corporation Systems Research, Center, Palo Alto, CA and Laboratory for Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts

4. IBM T.J. Watson Research Center, Yorktown, Heights, NY and Laboratory for Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts

Abstract

Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Alewife machine, a prototype implementation of the architecture, demonstrates that a parallel system can be both scalable and programmable. Four mechanisms combine to achieve these goals: software-extended coherent shared memory provides a global, linear address space; integrated message passing allows compiler and operating system designers to provide efficient communication and synchronization; support for fine-grain computation allows many processors to cooperate on small problem sizes; and latency tolerance mechanisms --- including block multithreading and prefetching --- mask unavoidable delays due to communication.Microbenchmarks, together with over a dozen complete applications running on the 32-node prototype, help to analyze the behavior of the system. Analysis shows that integrating message passing with shared memory enables a cost-efficient solution to the cache coherence problem and provides a rich set of programming primitives. Block multithreading and prefetching improve performance by up to 25% individually, and 35% together. Finally, language constructs that allow programmers to express fine-grain synchronization can improve performance by over a factor of two.

Publisher

Association for Computing Machinery (ACM)

Reference29 articles.

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3. A Survey on Trusted Distributed Artificial Intelligence;IEEE Access;2022

4. Fifer: Practical Acceleration of Irregular Applications on Reconfigurable Architectures;MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture;2021-10-17

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