Providing Accountability in Heterogeneous Systems-on-Chip

Author:

Kalayappan Rajshekar1ORCID,Sarangi Smruti R.2

Affiliation:

1. Indian Institute of Technology Dharwad and Indian Institute of Technology Delhi, India

2. Indian Institute of Technology Delhi, New Delhi, Delhi, India

Abstract

When modern systems-on-chip (SoCs), containing designs from different organizations, miscompute or underperform in the field, discerning the responsible component is a non-trivial task. A perfectly accountable system is one in which the on-chip component at fault is always unambiguously detected. The achievement of accountability can be greatly aided by the collection of runtime information that captures the events in the system that led to the error. Such information collection must be fair and impartial to all parties. In this article, we prove that logging messages communicated between components from different organizations is sufficient to provide accountability, provided the logs are authentic. We then construct a solution based on this premise, with an on-chip trusted auditing system to authenticate the logs. We present a thorough design of the auditing system, and demonstrate that its performance overhead is a mere 0.49%, and its area overhead is a mere 0.194% (in a heterogeneous 48 core, 400 mm 2 chip). We also demonstrate the viability of this solution using three representative bugs found in popular commercial SoCs.

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

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Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Development of a Power Electronics Controller with RISC-V based Core for Security-Critical Applications;2022 IEEE 63th International Scientific Conference on Power and Electrical Engineering of Riga Technical University (RTUCON);2022-10-10

2. A Formal Approach to Accountability in Heterogeneous Systems-on-Chip;IEEE Transactions on Dependable and Secure Computing;2021-11-01

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