Flow machine diagrams for VHDL code-Reference-Cited by-同舟云学术

Flow machine diagrams for VHDL code

Published:2017-03-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Second International Conference on Internet of things, Data and Cloud Computing
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Author:

Al-Fedaghi Sabah¹,Sultan Sari¹

Affiliation:

1. Kuwait University, Safat, Kuwait

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3018896.3056779

Reference22 articles.

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2. Zwagerman M. D. 2015. High Level Synthesis a Use Case Comparison with Hardware Description Language. Master's Thesis. Grand Valley State University. Zwagerman M. D. 2015. High Level Synthesis a Use Case Comparison with Hardware Description Language. Master's Thesis. Grand Valley State University.

3. Niedermeier A. 2014. A Fine-Grained Parallel Dataflow-Inspired Architecture for Streaming Applications. PhD Thesis Faculty of Electrical Engineering Mathematics and Computer Science University of Twente. Niedermeier A. 2014. A Fine-Grained Parallel Dataflow-Inspired Architecture for Streaming Applications. PhD Thesis Faculty of Electrical Engineering Mathematics and Computer Science University of Twente.

4. Model-driven development - Guest editor's introduction

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