Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration-Reference-Cited by-同舟云学术

Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration

Published:2022-06-06 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Great Lakes Symposium on VLSI 2022
language:
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Author:

Rashid Md Imtiaz¹,Carrion Schafer Benjamin¹

Affiliation:

1. The University of Texas at Dallas, Richardson, TX, USA

Funder

NATO

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3526241.3530339

Reference18 articles.

1. High-level synthesis design space exploration: Past, present and future;Carrion Schafer B.;IEEE TCAD,2019

2. B. Carrion Schafer , T. Takenaka , and K. Wakabayashi , " Adaptive simulated annealer for high level synthesis design space exploration," in VLSI-DAT , pp. 106 -- 109 , April 2009 . B. Carrion Schafer, T. Takenaka, and K. Wakabayashi, "Adaptive simulated annealer for high level synthesis design space exploration," in VLSI-DAT, pp. 106--109, April 2009.

3. Machine leaming to set meta-heuristic specific parameters for high-level synthesis design space exploration;Wang Z.;DAC,2020

4. Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching;Xydis S.;ISVLSI,2010

5. N. K. Pham , A. K. Singh , A. Kumar , and M. M. A. Khin , "Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis," in DATE, (New York, NY, USA) , ACM , 2014 . N. K. Pham, A. K. Singh, A. Kumar, and M. M. A. Khin, "Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis," in DATE, (New York, NY, USA), ACM, 2014.

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